AN736 vishay siliconix document number: 71351 03-may-01 www.vishay.com 1 a smart regulator design for network interface cards using the si91860 nitin kalje the advance configuration and power interface (acpi) specification minimizes power consumption in desktop and other pc systems and yet maintains full operation. the instantly available pc (iapc) is one aspect of power saving when the entire system is not required to be on. iapc maintains power to the critical circuitry to wake up the pc up from sleep mode at a power management event (pme) such as a phone?ring or a lan signal. the response to a pme might be to move the entire system, or specific devices, to the fully operational power state or to a lower power state, depending upon the event and the current power state. the vishay siliconix si91860 is a power ic specifically designed to regulate power for network interface cards (nic), pcmcia cards, and pci interface cards in desktop and notebook computers. the si91860 400-ma smart regulator combines an ultra-low supply current that reduces power consumption with a highly integrated design that that requires only four external components for a complete application circuit. pci cards are designed to support three different voltage sources ? the 5-v primary input (v in ), the 5-v standby input (v sb ) from the legacy pci system or motherboard, and the 3.3-v auxiliary supplies (v aux ). in sleep mode, the pci bus and its standard voltage rails are powered down, while the auxiliary 3.3-v supply remains on. the si91860 monitors each voltage supply and selects the supply most appropriate for delivering an uninterrupted, regulated, glitch-free 3.3-v output to the pci card chipset. the si91860 can handle 400-ma of continuous load current from any of the available power sources, providing a 25-ma headroom over the 375 ma required by the pci bus power management interface specification of 375 ma in enabled mode. si91860 operation: the si91860 consists of two 5-v to 3.3-v linear regulators, a low-resistance power switch, voltage monitors for the input supplies, and control logic. figure 1 provides the block diagram of the si91860. either of the two linear regulators can supply a constant 3.3-v output from the 5-v inputs. the total combined dropout across the regulator and switch is low enough to maintain the output regulation at a peak 600-ma load and minimum input voltage. irrespective of which input is used, the 3.3-v output is well regulated with dynamic line/load regulation and output voltage immunity to any input switchovers. figure 1. block diagram 5 v sb regulator driver 5 v sb 5, 6 7, 8 si91860 3.3 v out 3 5 v in regulator driver 5 v in logic control 3.3 v aux 1 2 4 4.7 f 4.7 f 4.7 f 2.2 f
AN736 vishay siliconix www.vishay.com 2 document number: 71351 03-may-01 figure 2. switching between inputs 50 ms/div 5 v in (5 v/div) 5 v in = 5 v 5 v sb = 5 v i out = 150 ma ch1 5 v in ? i/p current (200 ma/div) 5 v sb (5 v/div) 5 v sb ? i/p current (200 ma/div) the voltage levels on the v in and v sb are monitored and compared to a threshold voltage of 4.35 v. if the voltage on the input is above this threshold, the associated regulator may be enabled. logic circuitry enables the v in regulator over the v sb if both are present and valid. the 5-v standby regulator will be enabled provided that the voltage level is above the lockout threshold and the 5-v in input is not present. if neither of the 5-v inputs is above the lockout threshold, the 3.3-v v aux input powers the output through the bypass transistor. the waveforms in figure 2 illustrate the priority control in switching between the v in , v sb , and v aux input supplies. disturbances on the output resulting from the switchover from the main 5-v in input to the standby 5-v sb input, and vice versa, may be caused by delays in the control circuitry and amplifiers. the si91860 is designed to reduce their occurrence by minimizing delays during transitions. as shown in figures 3 through 6, the output is recovered within two microseconds during the switchovers from the 5-v in , 5-v sb , and 3.3-v aux inputs. the 5-v v in and 5-v v sb regulators use a p-channel power mosfet series element that reduces the power consumption of the si91860 by significantly reducing the ground current. mosfets provide higher peak drive currents than solutions using bipolar series elements, where the maximum current drawn is limited by the available base current. the 3.3-v v aux bypass switch has an on-resistance of just 0.2- ? , and drops only 80 mv at 400-ma load. the 3.3-v v aux gate threshold voltage of the bypass transistor is 0.8 v and needs a minimum of 2 v on the auxiliary input for a 400-ma output current. 5 v sb = 5 v 3.3 v aux = 0 v i out = 400 ma m 5.00 s/div m 5.00 s/div 5 v sb = 5 v 3.3 v aux = 0 v i out = 400 ma 3.3 v out (100 mv/div) 200 mv/div (offset = 5 v) 5 v in 5 v sb 3.3 v out (100 mv/div) 5 v in 5 v sb 500 mv/div (offset = 4.3 v) 200 mv/div (offset = 5 v) 500 mv/div (offset = 4.2 v) figure 3. 5-v in power up (5 v sb = 5 v) figure 4. 5-v in power down (5 v sb = 5 v) m 5.00 s/div 5 v sb = 0 v 3.3 v aux = 3.3 v i out = 400 ma 3.3 v out (100 mv/div) 3.3 v aux 200 mv/div (offset = 3.3 v) 500 mv/div (offset = 4.2 v) 5 v in figure 5. 5-v in power down (3.3 v aux = 3.3 v) figure 6. 5-v in power up (3.3 v aux = 3.3 v) m 5.00 s/div 5 v sb = 0 v 3.3 v aux = 3.3 v i out = 400 ma 3.3 v out (100 mv/div) 200 mv/div (offset = 3.3 v) 500 mv/div (offset = 4.3 v) 3.3 v aux
AN736 vishay siliconix document number: 71351 03-may-01 www.vishay.com 3 input voltage hysteresis: during power-up of the device, the circuit draws a high current to charge up the empty capacitor. the input inrush currents could be several times higher than the normal operating currents of the regulator. for the si91860, the inrush current during the power-up consists of two components: a) charging of the input capacitor, and b) the output load and charging of the output capacitor. the input capacitor, charging inrush current may be neglected if it is charged with the finite rise time of the source voltage. when the rising input voltage reaches the v in -select of 4.3 v, the si91860 turns on to charge the output capacitor while delivering the load current. the output capacitor is at this point charged with a 4.3-v differential and can produce very high current pulse for a short duration. the large input inrush current can produce a substantial voltage glitch if the inductive impedance of the input trace is not low enough. the si91860 is provided with a 230-mv hysterisis at the main and stand-by inputs to avoid any oscillations and system locking during start up. refer to figure 7 for the effect of source/trace impedance on the primary input. the si91860 is powered up through inductive and resistive impedance values of 125 nh and 50 m ? , respectively. figure 7. voltage glitch at 5 v in m 5.00 s/div v in = 0 ? 5 v v out = 3.3 v i out = 400 ma c in = 4.7 f c out = 2.2 f 200 mv/div (offset = 4.32 v) 5 v in v out (2 v/div) i 5vin (1 a/div) power dissipation/junction temperature: the 5-v v in and 5-v v sb are rated to deliver up to a 600-ma peak current for two milliseconds. the internal logic allows the current to be drawn from one regulator at a time. the maximum load current is specified for continuous operation and for finite pulse widths. maximum allowable junction temperature, junction-to-ambient thermal impedance at a thermal equilibrium, and the ambient temperature determine the continuous current rating at a given input-to-output dif ferential. the input voltage, p-channel power mosfet transconductance, and the transient thermal impedance between junction to lead are major issues for the peak current amplitude and pulse width. the maximum continuous power dissipation can be calculated using the following equation: p d 5v in 3.3 i out 5v in i gnd the worst-case scenario in minimum continuous power dissipation would occur at 5-v v in = 5 v sb = 5.5 v and i out = 400 ma. the si91860 does not draw any current from the 3.3-v v aux when the 5-v v in and 5-v v sb are present. refer to the si91860 datasheet for the typical values of the 5-v v in and 5-v v sb supply currents. the maximum continuous power dissipation of the si91860 can be calculated using the following equation: p dmax t jmax t amax ja the absolute maximum junction temperature allowed for si91860 is 150 c, while the junction-to-ambient thermal impedance is 62.5 c/w. the junction-to-ambient thermal impedance is measured with the device mounted and all leads soldered on the 1.6-mm glass epoxy fr4 pc board with a 1-oz copper area. short circuit / over temperature protection: in the event of a short circuit in the equipment powered by the 5-v v in and 5-v v sb , the si91860 limits the maximum current to prevent damage to the electronics. the peak current through the si91860 is typically limited to 800 ma during continuous short circuit at the output. in bypass mode, the device is not current limited. it is advised to limit the source current of the 3.3-v v aux in case of short circuit in the bypass mode. the si91860 is designed with an over-temperature protection circuit that prevents thermal runaways in the p-channel power mosfets. the si91860 will shut off and stop sourcing the current as soon as the junction temperature exceeds the over-temperature limit. if the junction temperature reaches 165 c, an internal control circuit shuts off the p-channel power mosfet. the si91860 will remain disabled until the chip temperature drops below 145 c, at which point it will turn on automatically. the 20 c temperature hysterisis avoids possible oscillation and minimizes the risk of damage by reducing the average power delivery during fault conditions.
AN736 vishay siliconix www.vishay.com 4 document number: 71351 03-may-01 m 5.00 s/div m 5.00 s/div v out = 50 mv/div i out = 200 ma/div input = 5 v in or 5 v sb i out = 0 to 400 ma t rise = 2 sec v out = 50 mv/div i out = 200 ma/div input = 5 v in or 5 v sb i out = 400 to 0 ma t fall = 2 sec figure 8. load transient response-1 figure 9. load transient response-2 loop compensation and load transient response: for stable operation of a closed loop electronic system, such as a voltage regulator, the feedback loop needs to be compensated to keep the total phase lag encountered at less than 360 c for a signal having a total gain greater than or equal to unity. the phase lag includes the 180 phase change caused by the negative feedback. the linear regulator closed loop has two poles. the first is a low-frequency pole (p 1 ) that results from the output capacitance (c out ) and the channel length modulation parameter of the p-channel mosfet. the location of this pole changes with the output load. the second pole (p 2 ) is introduced by the compensation capacitor, the parasitics of the series pass element, and the error amplifier of the regulator. the si91860 uses an internal zero to achieve a stable feedback loop that eliminates the need to rely on the esr value of the output capacitors. the location of the internal zero is changed to offset any effect of the load on the low-frequency pole, p 1 . this internal zero also offers the freedom to use a low-esr ceramic x5r or y5v capacitor for lower noise. as a result of the internal compensation of the si91860, a closed-loop bandwidth as high as 100 khz is achieved with approximately a 60 phase margin. high closed-loop bandwidth, along with a sufficient phase margin, results in a good dynamic load response. with a closed-loop bandwidth of 100 khz or more, the si91860 needs a lower output capacitor for a given dynamic load response performance. also, the freedom to use a very low esr ceramic capacitor further reduces the form factor for enhanced performance. the output voltage drop is the result of output capacitance, the esr of the output capacitance, and the response time of the device for a given step load. with a 2- s slew rate step load from zero to 400 ma, the output drops by less than 50 mv and recovers to the regulated voltage in less than 5 s. refer to figures 8 and 9 for the transient load response with a 2.2- f ceramic capacitor at the output. v i step t response c out i step esr where: i step = output step load (a) esr = esr of output capacitor (w) t response = response time of the regulator (s) t response depends on the unity gain bandwidth and the phase margin of the closed loop. input capacitor selection: the input capacitor selection is dominated by the source impedance, the resistive and inductive impedance of the trace, the rising edge hysterisis, the output capacitance, and the maximum load. the input bypass capacitor, located close to the si91860, supports short glitches of about one microsecond. a 4.7- f to 10- f ceramic capacitor with y5v dielectric is recommended for a small, low-cost solution. an x5r dielectric is recommended for better temperature characteristics. minimizing the source trace inductance reduces the capacitance requirement.
AN736 vishay siliconix document number: 71351 03-may-01 www.vishay.com 5 pcb layout: the component placement around the si91860 should be done carefully to achieve good dynamic line and load response. the input and output capacitors should be kept close to the si91860. the rise in junction temperature depends on how efficiently the heat is carried away from the junction to the ambient. the junction-to-lead thermal impedance is a characteristic of the package and is fixed. by increasing the size of the copper area on the pcb, lead-to-ambient thermal impedance can be reduced. increase the ground trace area to reduce the junction-to-ambient thermal impedance. although the si91860 is provided with the input hysterisis, the system can break into oscillations if the input impedance is not low enough. the input trace inductance and resistance should be kept low to achieve overall input impedance of the source at the input of the si91860. wide traces from source to the primary, standby, and auxiliary inputs are recommended, with a large ground plane for the ground connection. for a turn-on rise time ( t) and the input inrush current ( i), the maximum trace/source inductance and resistance that could be tolerated can be estimated using the following equation: v glitch (l trace ( max ) i t r i ) l = trace inductance (h) r = source plus trace resistance ( ) the expected v glitch should be less than the rising edge hysterisis of the 5-v v in and 5-v v sb . refer to figure 7 for an example of the observed glitch at the input terminal with a 0.05- source plus trace resistance and a125-nh trace inductance. (5-inches long trace would have approximately 125-nh inductance.)
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